The relentless pursuit of faster and more energy-efficient computing has hit a fundamental barrier in conventional transistors, but a research team at The Hong Kong Polytechnic University (PolyU) has unveiled a novel device that could redefine the future of microelectronics. Their breakthrough, published in the prestigious journal Science, demonstrates a tunnelling field-effect transistor (TFET) that surpasses the long-standing 'Boltzmann limit', a physical constraint that has limited energy efficiency in traditional semiconductors.
For decades, transistor scaling has driven the exponential growth of computing power. However, as devices shrink to atomic dimensions, engineers face a daunting challenge: the Boltzmann limit, which dictates that at room temperature, the subthreshold swing (SS) – a measure of how sharply a transistor switches between on and off states – cannot drop below 60 millivolts per decade (mV/dec). This limit arises from the thermionic emission of charge carriers, a process that requires a minimum gate voltage to control current flow. The inability to lower SS below this threshold has stymied efforts to reduce power consumption without sacrificing performance.
Prof. Jianhua Hao, Head of the Department of Physics and Materials and Chair Professor of Materials Physics and Devices at PolyU, along with collaborators from the National University of Singapore, The Hong Kong University of Science and Technology, Peking University, and the Singapore University of Technology and Design, have engineered a TFET that leverages quantum tunnelling to circumvent this limit. 'By adopting quantum tunnelling, our TFET breaks through this boundary, paving the way for ultra-low-power, high-performance integrated circuits essential for emerging AI chips and advanced semiconductor applications,' said Prof. Hao.
The key to their innovation lies in a meticulously crafted heterostructure composed of alternating layers of 2D bismuth and indium selenide, deposited using pulsed laser deposition. This technique allows precise control over the layer thickness and interface, transforming bismuth – normally a semi-metal – into a semiconductor when reduced to a 2D form. This transformation enables charge carriers to efficiently tunnel through the thin barrier into the indium selenide layer, a quantum-mechanical process that bypasses the thermionic bottleneck.
The resulting TFET achieved SS values well below the 60 mV/dec limit, operating at room temperature on silicon substrates. Moreover, the device required a gate voltage swing of only 160 mV, a five-fold reduction compared to the 800 mV typically needed in conventional transistors. This dramatic improvement in energy efficiency is complemented by a high output current and an exceptionally high ON/OFF current ratio, which are critical for driving multiple downstream logic gates and reducing circuit delays.
The implications of this work are profound. As artificial intelligence and data-centric applications demand ever greater computational power, the energy consumption of current chips becomes unsustainable. By offering a pathway to ultra-low-power transistors, this research could enable a new generation of AI accelerators and mobile devices that operate for longer on a single charge, while also reducing the environmental footprint of data centers.
The breakthrough also underscores the potential of 2D materials in post-silicon electronics. While the study represents a proof-of-concept, the team's approach of using scalable deposition methods on silicon substrates suggests a viable route toward commercial integration. As the semiconductor industry grapples with the limits of Moore's law, innovations like this TFET could provide the foundational technology for the next era of computing.
